MOS Technology 8502

The MOS Technology 8502 is the 8-bit 6502-family processor that serves as the Commodore 128 (C128)'s main processor in native C128 and C64-compatible operation. The same computer also contains a Zilog Z80 for CP/M mode, so the 8502 is best understood as one side of a controlled two-processor system rather than as the C128's only processor. Its selectable clock rate, its sharing of the system bus with video and I/O hardware, and its hand-off relationship with the Z80 are therefore central to describing what “2 MHz” means on a C128.

Design and place in the C128

The 8502 retains the 6502-compatible programming model used by the C128's predecessor family; contemporary C128 documentation characterizes it as software-compatible with both the 6502 and the 6510. This compatibility is why C64-oriented 65xx machine-language conventions remain relevant when the C128 runs its compatible mode, even though the installed processor is an 8502.

The C128 documentation gives the 8502 two nominal operating rates, approximately 1.02 MHz and 2.04 MHz. In C64 mode the published configuration is 1.02 MHz, while native C128 software can request the higher rate; the user-facing `FAST` command exposes that choice and `SLOW` restores the lower-rate display-oriented mode. The rate selection is consequently a system-state decision, not a promise that every operation in a program is executed at the high rate.

The 8502 is therefore neither simply a relabelled C64 processor nor an isolated accelerator. Its value to the C128 is continuity: familiar 65xx software can run in a machine that has additional memory-management, display, and operating-mode facilities. Its behavior is also conditional on those facilities. The processor's instruction execution must coexist with the video controller's access to dynamic RAM, the timing expectations of I/O chips, and a second CPU that can be granted the system bus.

A C128 Memory Management Unit (MMU) participates in both mode selection and processor selection. The independent C128 internals account describes the MMU as choosing among C64, C128, and CP/M modes as well as between the 8502 and Z80, and the VICE emulator's MMU implementation likewise changes its active CPU when the mode-configuration state changes. This is a hardware-managed division of roles, not simultaneous execution on a shared bus: Commodore's service documentation says that only one processor can own that bus at a time.

The service account also explains why the Z80 is initially allowed to take control during startup before it enables the 8502 for the selected C128 or C64 path. The early Z80 code and the later 8502 operating path should thus not be collapsed into a claim that the machine boots straight into ordinary 8502 execution.

The distinction is useful when interpreting C128 documentation that calls the 8502 the “main” processor. That label identifies the processor used for the ordinary native and compatible 65xx environments; it does not mean that the Z80 is electrically absent, nor that both chips run programs at once. The system retains the state necessary to pass control from one processor to the other, but serializes their access to the shared bus.

Clock modes and video constraints

The C128 powers up with the 8502 at the lower rate. Selecting `FAST` requests the 2 MHz operating mode, but it also removes the 40-column VIC display from normal display work; graphics data can still be prepared, yet that display is not shown until slow operation returns. At the hardware level, the service manual attributes this trade-off to the VIC: in 2 MHz mode it ceases to act as the display processor, while processor bus time is made available and the VIC continues refresh and arbitration duties.

The documented control is bit 0 of register 48 in the 8564 VIC. Setting it enables the high-rate condition and clearing it restores the 1 MHz condition in which the VIC can resume display processing. This register-level fact matters because it separates an intentional timing mode from a benchmark-style property of the 8502 alone. The processor can be clocked faster only within the C128's coordinated VIC and bus design.

This does not make the entire machine a permanently 2 MHz system. The 8564's I/O-access indication causes the high-rate clock to be stretched so that devices designed around the 1 MHz timing remain synchronized; the service documentation accordingly treats most bus and all I/O timing as tied to the 1 MHz reference. Refresh and I/O access therefore force the slow timing even when high-rate operation has been selected. This limitation also explains the programming guidance that operations involving the documented DMA facilities must occur in slow mode.

As a result, “2 MHz mode” is most precise when it describes the selected 8502 clock condition during work that does not require a slow-timed I/O access or VIC 40-column display activity. A program may switch modes around its work, but it cannot infer that a requested rate changes the timing contract of every chip on the board. This is also why nominal processor frequency alone is an incomplete comparison between C128 modes or between the C128's two processors.

The restriction concerns the VIC's 40-column display path rather than every video facility in the computer. The C128 documentation distinguishes the 8564/VIC 40-column output from the 8563 80-column controller, and the service manual describes 2 MHz operation with the 80-column display path in use while the VIC display function is disabled. For software, “fast” is consequently a useful description only when the selected video path and any imminent I/O access are included in the description.

Alongside the Z80

The Z80 gives the C128 its CP/M execution mode, while Commodore's programmer reference assigns the 8502 the native C128 and C64 roles and explicitly identifies it as I/O support for CP/M. The processors exchange control through the system's bus-arbitration logic. When the controlling MMU signal requests the 8502, the Z80 performs the bus-request/acknowledge behavior for which the Z80 architecture provides high-impedance bus release; the C128 service manual identifies the resulting BUSACK, AEC, and RDY sequence as the processor-switch mechanism.

CP/M mode therefore does not mean that the 8502 disappears from the machine's operational design. The service manual says that a Z80 program can transfer an I/O task to 8502 KERNAL routines when that task is not supplied by the Z80 BIOS. Preserved C128 CP/M build material separately assembles and adds a component named `FAST8502`, and that component is identified as 8502 drivers and routes disk and channel operations through C128 KERNAL entry points; this source-level record is consistent with the service description of delegated I/O, without requiring the source text to be reproduced here.

The build record is particularly useful corroboration because it distinguishes a general statement about “two CPUs” from a concrete CP/M system composition. It records a separately built 8502 support element added to the generated CP/M system, while its accompanying source labels that element as 8502 drivers and uses C128 KERNAL service entry points for channel and disk activity. It does not show two processors sharing the bus concurrently; rather, it is evidence that CP/M software can rely on an 8502-side service component within the hand-off model described by the service documentation.

Clock terminology for the Z80 deserves the same care as it does for the 8502. The programmer reference lists the Z80 in CP/M mode at 2.04 MHz, whereas the service manual describes a 4 MHz Z80 clock that is present only during the low half of the 1 MHz clock. These are not competing descriptions of two different C128 Z80s: the former states the published operating rate, while the latter specifies the gated clock waveform that helps explain the effective timing context.

The hardware switching sequence is correspondingly more important than a simplified picture of a processor “taking over.” The C128 service manual relates the MMU's Z80-enable signal to the Z80's bus-request input and describes BUSACK, 8502 AEC, and RDY behavior during the hand-off. Zilog's CPU documentation independently describes BUSRQ/BUSACK as the protocol that releases the Z80's address, data, and control lines for external control. Together, these sources support treating the C128's CPU change as a coordinated bus transaction rather than an unqualified software jump.

Practical interpretation

For native C128 code, the 8502 is the processor that normally executes 65xx-compatible software and can obtain the faster rate when VIC 40-column display work is set aside. For C64-compatible work, its documented rate and surrounding configuration preserve the slower compatibility-oriented environment. For CP/M, the Z80 executes the CP/M-facing workload, but the 8502 remains part of the system's service path and is reached through ordered processor hand-offs rather than parallel bus ownership.

This framing avoids two common overstatements. It is inaccurate to describe the 8502 as continuously operating at 2 MHz whenever native mode is active, because the video and I/O rules qualify its effective timing. It is also incomplete to describe CP/M as “the Z80 mode” without noting the 8502's documented I/O-support role and the controlled transfer of the shared bus. The C128's processor architecture is most clearly described as a 65xx-centered native/compatible environment, supplemented by a Z80 CP/M environment and joined by purpose-built clock, memory-management, and arbitration logic.

This division also preserves an important analytical boundary: processor selection, video selection, and clock selection are related controls, but they are not interchangeable names for one setting. The C128 documentation describes each through particular MMU or VIC functions and through the resulting bus behavior.

See also

• Commodore 128
• MOS Technology 6510
• Commodore 64 memory map
• Zilog Z80
• CP/M
• VIC-II
• Memory Management Unit
• Commodore 1571

Automation and sourcing note

This article was independently synthesized from the cited sources under c64.wiki publication policy. Historical manuals and source archives were used as citation-only factual evidence; no source prose, code, images, scans, or screenshots were copied into the candidate.