MOS Technology 6510

The MOS Technology 6510 is the 8-bit microprocessor used as the central processor in the Commodore 64 (C64). It retains the 6502 programming model and instruction compatibility while adding an on-chip, bit-programmable parallel port. In the C64, that port is not a general-purpose extra for applications: its lower lines participate in selecting the CPU-visible memory configuration, and its other connected lines support the cassette interface.

6502-compatible design

The 6510 belongs to the 6502 line in the practical sense that software written for the documented 6502 instruction architecture can execute on it without the port changing the instruction set. It has an 8-bit data bus and a 16-bit address bus, so its processor-visible address space comprises 65,536 byte locations. This combination is why C64 machine-language programming is ordinarily described with 6502 registers, addressing modes, and instructions even though the installed processor is a 6510.

The port is the material architectural addition for the C64. The generic manufacturer sheet describes an eight-bit port and shows related package variants, whereas the C64 documentation and C64-specific pinout accounts show six connected processor-port lines, P0–P5. This should be read as a distinction between family-level documentation and the C64's implemented package and wiring, rather than as evidence for two incompatible C64 designs. The C64 processor operates near one megahertz, with the precise nominal rate differing between PAL and NTSC machines.

Place in the Commodore 64

The C64 combines 64 KiB of RAM with BASIC ROM, KERNAL ROM, character ROM, I/O devices, and possible cartridge resources, but the processor can present only a 64 KiB address space at one time. The system therefore uses overlays: at certain address ranges, the selected responder can be RAM, ROM, or I/O rather than a permanently unique physical memory device. The 6510's port supplies three of the control signals that the C64's programmable logic array (PLA) combines with address and cartridge signals to make those selections.

This arrangement makes the 6510 part of the C64's memory-management mechanism, even though it has no separate memory-management unit. Port line P0 is associated with LORAM, P1 with HIRAM, and P2 with CHAREN; through the PLA, these signals govern the usual visibility of BASIC ROM at $A000–$BFFF, KERNAL ROM at $E000–$FFFF, and I/O versus character ROM in the $D000–$DFFF window. Cartridge control lines can also influence the result, so the same processor-port bit pattern is not the whole memory map in every hardware configuration. The CPU's role is consequently both conventional—fetching and executing instructions—and configurational, because a program can change what later CPU reads and writes reach.

The ordinary C64 configuration is therefore a selected view, not a claim that the ROM and I/O areas displace the machine's RAM permanently. With the customary settings, firmware and I/O are convenient to use, while changing the port can expose RAM in areas that normally respond as BASIC ROM, KERNAL ROM, or the $D000 window. This is a board-level selection process: the port does not copy data between memories, and the PLA rather than the 6510 alone performs the decoding that enables a selected responder. Consequently, a memory address in a C64 program names a location within a configuration, not necessarily one unchanging physical chip.

On-chip port and registers

The port is controlled through two special locations at the start of the CPU address space. Address $0000 is the data-direction register and $0001 is the port data register; direction is individually selectable by bit. Programs must distinguish those registers: writing a bit value to $0001 does not drive a port line unless the corresponding direction bit has been configured as an output. On the C64, only the low six bits are significant for the processor-port connections described by the board documentation.

The three low lines are shared system controls rather than spare user I/O. Altering them can reveal RAM beneath a ROM or I/O overlay, select the character ROM for CPU reads, or restore the ordinary firmware-and-I/O layout. Because I/O registers and character ROM occupy the same CPU address window under different selections, code that switches the window away from I/O cannot simultaneously use the device registers located there. A temporary configuration change thus needs to preserve enough executable code and data in the selected view to return safely to the desired configuration.

The remaining connected lines serve the cassette subsystem. C64-specific references identify P3 as cassette data output, P4 as cassette switch sense, and P5 as cassette motor control. The board schematic independently places these processor-port connections on the cassette-related circuitry, while the lower three lines lead to the PLA inputs. Tape input timing is not handled by the port alone: the C64OS schematic analysis traces the cassette read path through CIA 1 and its interrupt path, so the CPU port should not be mistaken for the complete cassette interface.

Bus participation and programming consequences

The 6510 also has an address-enable control input. When that signal is inactive, the processor's address, data, and read/write outputs enter a high-impedance state; the manufacturer describes this as support for direct memory access and shared-bus systems. In the C64, the board-level account identifies this capability as the means by which the CPU can be decoupled while another chip takes control of the bus. This is important in a graphics computer because CPU operation is coordinated with other chips rather than occurring on an electrically private bus.

For programmers, the lasting significance of the 6510 is that $0000 and $0001 are live hardware state, not ordinary scratch bytes. Software that changes the port must account for the data-direction register, the selected memory view, cartridge inputs where relevant, and the need to restore a configuration expected by firmware or a caller. The 6510 therefore preserves 6502-compatible programming while binding that programming model tightly to the C64's ROM, I/O, cassette, and bus-sharing design.

See also

• Commodore 64
• Commodore 64 memory map
• MOS Technology 6502
• KERNAL
• Commodore 64 BASIC
• VIC-II
• SID
• MOS Technology 6526 CIA
• Commodore 64 cartridge
• Datassette
• Zero page

Automation and sourcing note

This candidate was independently synthesized from the cited sources under c64.wiki publication policy. It contains no copied manual prose, scans, images, screenshots, or source-code extracts; historical manuals and schematics are cited as evidence only.